Re: PCI bus master with Prism2.5 (was: High CPU utilization of hostap)

From: Jouni Malinen (
Date: 2002-05-07 14:10:28 UTC

On Mon, May 06, 2002 at 09:42:52PM +0300, Jouni Malinen wrote:

> It looks like this can be done on Prism2.5 PCI cards. However, it is
> more or less undocumented and unsupported..

I got confirmation about this.. It is not supported at all (not even implemented according to Intersil support). Well, since I did get it working at least partially, I might add support for this to the driver, but it would probably not be enabled in the default version since I have no idea whether it works on all Prism2.5 PCI cards or if there are some problems that do not occur in my test setup.

> The card seems to handle ping floods for some time, but continued ping
> flood (or even short UDP flood with more packets) seems to be enough
> to kill it. This causes hwreset, which seems to success but the host
> dies shortly after this for some unknown reason..

That crash after hwreset was a small bug in my test driver. In addition, SWSUPPORT0 register seems to return 0000 sometimes during bus master use, so I removed that verification from prism2_interrupt() when using PCI cards with bus mastering. After these changes, I have been able to flood the PCI card with large ping packets and UDP/TCP without crashes or timeouts, so major problems on RX path seem to be solved.

According to initial performance tests, using bus mastering is a huge improvement. System load during UDP flood (with large packets) varied from 38% to 45% with the normal copy from BAP transfer used in the released driver. Identical test using bus mastering produced system loads between 4% and 7%.

TX path needs some more work with locking since BAP0 was previously not used at all from hard interrupts. Otherwise separating BAP transfer from prism2_tx() should be quite easy.

On Mon, May 06, 2002 at 06:11:19PM -0700, John D. Rowell wrote:

> Any chance that there's a better way of doing this in hostap_cs also?

This is bit problematic.. There's probably some kind of DMA controller on Intel chipset, but it might not be at all usable with ioports on Intel platforms.

Prism2.5 PCI cards use memory mapped registers and in addition I'm using the bus master on the Prism2.5 card for BAP transfer. My current assumption is that similar thing cannot be done with Prism2-based PC Cards at least on generic Intel platforms. However, using some other platform that uses memory mapping for the ioports might have better change of succeeding.

Jouni Malinen                                            PGP id EFC895FA

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